Power Modelling of 3D-Stacked Memories with TLM2.0 based Virtual Platforms
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چکیده
Three-dimensional stacked Wide I/O DRAMs have been proposed as a promising solution to overcome the pin-limited memory performance growth, the power vs. bandwidth dilemma and the Memory Wall. This new DRAM architecture and organisation requires a new generation of DRAM memory controllers. Virtual platforms enable us to explore the complete design space of memory controllers with an accurate power modelling at the system level with very fast simulation speeds and precise timing accuracy. In this paper, we present a virtual platform based on Synopsys Platform Architect for a fast and precise power estimation of multi-channel Wide I/O DRAMs.
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تاریخ انتشار 2013